linux-kernel - Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to msr-info.h

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Message-ID: <alpine.DEB.2.20.1610271629010.4817@nanos>
Date:   Thu, 27 Oct 2016 16:32:30 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
cc:     mingo@...hat.com, "H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        bp@...e.de, dave.hansen@...ux.intel.com, lukasz.daniluk@...el.com,
        james.h.cownie@...el.com,
        "Pan, Jacob jun" <jacob.jun.pan@...el.com>, Piotr.Luc@...el.com,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6: 1/4] x86/msr: Add R3MWAIT register and bit to
 msr-info.h

On Thu, 27 Oct 2016, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) has MSR
> MISC_THD_FEATURE_ENABLE 0x140.

Oh well. I just reviewed another patch which names this register:

   MSR_MISC_FEATURE_ENABLES

and that's how it's named in this document:

http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
 
Can Intel please get its act together and document that register proper in
the SDM?

Thanks,

	tglx