linux-kernel - RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot

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Message-ID: <ED52C51D9B87F54892CE544909A13C6C1FF65B38@IRSMSX101.ger.corp.intel.com>
Date:   Thu, 27 Oct 2016 16:53:45 +0000
From:   "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@...el.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "bp@...e.de" <bp@...e.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "Daniluk, Lukasz" <lukasz.daniluk@...el.com>,
        "Cownie, James H" <james.h.cownie@...el.com>,
        "Pan, Jacob jun" <jacob.jun.pan@...el.com>,
        "Luc, Piotr" <Piotr.Luc@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v6: 2/4] x86: Add enabling of the R3MWAIT during boot

> >  	init_intel_energy_perf(c);
> > +
> > +	/*
> > +	* Setting ring 3 MONITOR/MWAIT for thread
> > +	* when CPU is Xeon Phi Family x200 (KnightsLanding).
> > +	*/
> > +	if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL)
>
> Please move this conditional into the probe function.
>
> > +		probe_xeon_phi_r3mwait(c);
>
> Can you please check with your hardware people, whether this function is somewhere detectable. bit 0 of the MISC_*FEATURE* MSR (Ring 3 CPUID fault
> enable) is detectable via the PLATFORM_INFO MSR. I would be surprised if this thing is not detectable in some way.
>
> I really prefer detectable things over hardcoded crap which depends on model information.

I asked hardware people and MSR 0x140 should be called MSR_MISC_FEATURE_ENABLES and there is no other feature MSR indicating that this bit can be set. 
Unfortunately hardcoded crap has to be used.