linux-kernel - [PATCH v3 15/46] perf/x86/intel: encapsulate rmid and closid updates in pqr cache

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1477787923-61185-16-git-send-email-davidcc@google.com>
Date:   Sat, 29 Oct 2016 17:38:12 -0700
From:   David Carrillo-Cisneros <davidcc@...gle.com>
To:     linux-kernel@...r.kernel.org
Cc:     "x86@...nel.org" <x86@...nel.org>, Ingo Molnar <mingo@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Andi Kleen <ak@...ux.intel.com>,
        Kan Liang <kan.liang@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Vegard Nossum <vegard.nossum@...il.com>,
        Marcelo Tosatti <mtosatti@...hat.com>,
        Nilay Vaish <nilayvaish@...il.com>,
        Borislav Petkov <bp@...e.de>,
        Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Paul Turner <pjt@...gle.com>,
        Stephane Eranian <eranian@...gle.com>,
        David Carrillo-Cisneros <davidcc@...gle.com>
Subject: [PATCH v3 15/46] perf/x86/intel: encapsulate rmid and closid updates in pqr cache

Encapsulate updates for PQR_ASSOC msr's RMID and CLOSID into
intel_rdt_common. Use new interface in Intel CMT.

Change RDT common code to build for both CONFIG_INTEL_RDT_A and
CONFIG_INTEL_RDT_M.

Signed-off-by: David Carrillo-Cisneros <davidcc@...gle.com>
---
 arch/x86/events/intel/cmt.c             |  6 ++++++
 arch/x86/include/asm/intel_rdt_common.h | 30 ++++++++++++++++++++++++++++--
 arch/x86/kernel/cpu/Makefile            |  3 ++-
 arch/x86/kernel/cpu/intel_rdt_common.c  |  8 ++++++++
 4 files changed, 44 insertions(+), 3 deletions(-)
 create mode 100644 arch/x86/kernel/cpu/intel_rdt_common.c

diff --git a/arch/x86/events/intel/cmt.c b/arch/x86/events/intel/cmt.c
index 86c3013..ce5be74 100644
--- a/arch/x86/events/intel/cmt.c
+++ b/arch/x86/events/intel/cmt.c
@@ -4,6 +4,7 @@
 
 #include <linux/slab.h>
 #include <asm/cpu_device_id.h>
+#include <asm/intel_rdt_common.h>
 #include "cmt.h"
 #include "../perf_event.h"
 
@@ -1118,11 +1119,16 @@ static int intel_cmt_hp_online_enter(unsigned int cpu)
 	return 0;
 }
 
+/* Restore CPU's pqr_cache to initial state. */
 static int intel_cmt_hp_online_exit(unsigned int cpu)
 {
+	struct intel_pqr_state *state = per_cpu_ptr(&pqr_state, cpu);
 	struct pkg_data *pkgd;
 	u16 pkgid = topology_logical_package_id(cpu);
 
+	pqr_cache_update_rmid(0);
+	memset(state, 0, sizeof(*state));
+
 	rcu_read_lock();
 	pkgd = rcu_dereference(cmt_pkgs_data[pkgid]);
 	if (pkgd->work_cpu == cpu)
diff --git a/arch/x86/include/asm/intel_rdt_common.h b/arch/x86/include/asm/intel_rdt_common.h
index b31081b..1d5e691 100644
--- a/arch/x86/include/asm/intel_rdt_common.h
+++ b/arch/x86/include/asm/intel_rdt_common.h
@@ -1,13 +1,21 @@
 #ifndef _ASM_X86_INTEL_RDT_COMMON_H
 #define _ASM_X86_INTEL_RDT_COMMON_H
 
+#if defined(CONFIG_INTEL_RDT_A) || defined(CONFIG_INTEL_RDT_M)
+
+#include <linux/types.h>
+#include <asm/percpu.h>
+#include <asm/msr.h>
+
 #define MSR_IA32_PQR_ASSOC	0x0c8f
 
+
 /**
  * struct intel_pqr_state - State cache for the PQR MSR
  * @rmid:		The cached Resource Monitoring ID
+ * @next_rmid:		Next rmid to write to hw
  * @closid:		The cached Class Of Service ID
- * @rmid_usecnt:	The usage counter for rmid
+ * @next_closid:	Next closid to write to hw
  *
  * The upper 32 bits of MSR_IA32_PQR_ASSOC contain closid and the
  * lower 10 bits rmid. The update to MSR_IA32_PQR_ASSOC always
@@ -18,10 +26,28 @@
  */
 struct intel_pqr_state {
 	u32			rmid;
+	u32			next_rmid;
 	u32			closid;
-	int			rmid_usecnt;
+	u32			next_closid;
 };
 
 DECLARE_PER_CPU(struct intel_pqr_state, pqr_state);
 
+static inline void pqr_cache_update_rmid(u32 rmid)
+{
+	struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
+
+	state->next_rmid = rmid;
+	wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, state->closid);
+}
+
+static inline void pqr_cache_update_closid(u32 closid)
+{
+	struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
+
+	state->next_closid = closid;
+	wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, state->closid);
+}
+
+#endif
 #endif /* _ASM_X86_INTEL_RDT_COMMON_H */
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index cf4bfd0..b095e65 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -34,7 +34,8 @@ obj-$(CONFIG_CPU_SUP_CENTAUR)		+= centaur.o
 obj-$(CONFIG_CPU_SUP_TRANSMETA_32)	+= transmeta.o
 obj-$(CONFIG_CPU_SUP_UMC_32)		+= umc.o
 
-obj-$(CONFIG_INTEL_RDT_A)	+= intel_rdt.o
+obj-$(CONFIG_INTEL_RDT_A)	+= intel_rdt.o intel_rdt_common.o
+obj-$(CONFIG_INTEL_RDT_M)	+= intel_rdt_common.o
 
 obj-$(CONFIG_X86_MCE)			+= mcheck/
 obj-$(CONFIG_MTRR)			+= mtrr/
diff --git a/arch/x86/kernel/cpu/intel_rdt_common.c b/arch/x86/kernel/cpu/intel_rdt_common.c
new file mode 100644
index 0000000..7fd5b20
--- /dev/null
+++ b/arch/x86/kernel/cpu/intel_rdt_common.c
@@ -0,0 +1,8 @@
+#include <asm/intel_rdt_common.h>
+
+/*
+ * The cached intel_pqr_state is strictly per CPU and can never be
+ * updated from a remote CPU. Functions that modify pqr_state
+ * must ensure interruptions are handled properly.
+ */
+DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
-- 
2.8.0.rc3.226.g39d4020