linux-kernel - [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context

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Message-ID: <alpine.DEB.2.00.1610310345580.31859@tp.orcam.me.uk>
Date:   Mon, 31 Oct 2016 16:26:24 +0000
From:   "Maciej W. Rozycki" <macro@...tec.com>
To:     Ralf Baechle <ralf@...ux-mips.org>
CC:     <linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 2/4] MIPS: Remove FIR from ISA I FP signal context

Complement commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.") 
and remove the Floating Point Implementation Register (FIR) from the FP 
register set recorded in a signal context with MIPS I processors too, in 
line with the change applied to r4k_fpu.S.

The `sc_fpc_eir' slot is unused according to our current ABI and the FIR 
register is read-only and always directly accessible from user software.

Signed-off-by: Maciej W. Rozycki <macro@...tec.com>
---
linux-mips-isa1-sig-fp-context-dsp.patch
Index: linux-sfr-test/arch/mips/kernel/r2300_fpu.S
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/r2300_fpu.S	2016-10-22 02:17:38.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/r2300_fpu.S	2016-10-22 02:19:40.565112000 +0100
@@ -64,13 +64,9 @@ LEAF(_save_fp_context)
 	EX(swc1 $f29,(SC_FPREGS+232)(a0))
 	EX(swc1 $f30,(SC_FPREGS+240)(a0))
 	EX(swc1 $f31,(SC_FPREGS+248)(a0))
-	EX(sw	t1,(SC_FPC_CSR)(a0))
-	cfc1	t0,$0				# implementation/version
 	jr	ra
+	 EX(sw	t1,(SC_FPC_CSR)(a0))
 	.set	pop
-	.set	nomacro
-	 EX(sw	t0,(SC_FPC_EIR)(a0))
-	.set	macro
 	END(_save_fp_context)

 /*