[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <1478020482-231459-1-git-send-email-bin.gao@intel.com>
Date: Tue, 1 Nov 2016 10:14:40 -0700
From: Bin Gao <bin.gao@...el.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, H Peter Anvin <hpa@...or.com>,
x86@...nel.org
Cc: Peter Zijlstra <peterz@...radead.org>,
linux-kernel@...r.kernel.org, Bin Gao <bin.gao@...el.com>
Subject: [PATCH 0/2] x86/tsc: split X86_FEATURE_TSC_RELIABLE into two
This patch series split X86_FEATURE_TSC_RELIABLE into two separate
flags: X86_FEATURE_TSC_RELIABLE and X86_FEATURE_TSC_KNOWN_FREQ.
This change allows us to redefine TSC features at fine granularity.
This is driven by certain Intel processors/SoCs with frequency-known
TSC so the whole calibration stuff should be skipped.
Bin Gao (2):
x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/tsc.c | 15 ++++++++++++---
arch/x86/kernel/tsc_msr.c | 4 ++++
arch/x86/platform/intel-mid/mfld.c | 5 +++--
arch/x86/platform/intel-mid/mrfld.c | 4 ++--
5 files changed, 22 insertions(+), 7 deletions(-)
--
1.9.1
Powered by blists - more mailing lists