linux-kernel - Re: [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value for ddr pll

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Message-ID: <20161102012751.GF16026@codeaurora.org>
Date:   Tue, 1 Nov 2016 18:27:51 -0700
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Abhishek Sahu <absahu@...eaurora.org>
Cc:     andy.gross@...aro.org, david.brown@...aro.org, robh+dt@...nel.org,
        pawel.moll@....com, mark.rutland@....com,
        ijc+devicetree@...lion.org.uk, mturquette@...libre.com,
        galak@...eaurora.org, pradeepb@...eaurora.org,
        mmcclint@...eaurora.org, varada@...eaurora.org,
        sricharan@...eaurora.org, architt@...eaurora.org,
        ntelkar@...eaurora.org, linux-arm-msm@...r.kernel.org,
        linux-soc@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v3 6/7] clk: qcom: ipq4019: changed the frequency value
 for ddr pll

On 09/21, Abhishek Sahu wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
> index b2decd5..a2809db 100644
> --- a/drivers/clk/qcom/gcc-ipq4019.c
> +++ b/drivers/clk/qcom/gcc-ipq4019.c
> @@ -546,7 +546,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
>  	F(25000000,  P_FEPLL500, 1,  1, 20),
>  	F(50000000,  P_FEPLL500, 1,  1, 10),
>  	F(100000000, P_FEPLL500, 1,  1, 5),
> -	F(190000000, P_DDRPLL,   1,  0, 0),
> +	F(192000000, P_DDRPLL,   1,  0, 0),

Change from 193 to 190 to 192.... please do it once.

>  	{ }
>  };
>  
> @@ -567,18 +567,18 @@ static struct clk_rcg2  sdcc1_apps_clk_src = {
>  static const struct freq_tbl ftbl_gcc_apps_clk[] = {
>  	F(48000000,  P_XO,         1, 0, 0),
>  	F(200000000, P_FEPLL200,   1, 0, 0),
> -	F(380000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(409000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(444000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(484000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(384000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(413000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(448000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(488000000, P_DDRPLLAPSS, 1, 0, 0),
>  	F(500000000, P_FEPLL500,   1, 0, 0),
> -	F(507000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(532000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(560000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(592000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(626000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(666000000, P_DDRPLLAPSS, 1, 0, 0),
> -	F(710000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(512000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(537000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(565000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(597000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(632000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(672000000, P_DDRPLLAPSS, 1, 0, 0),
> +	F(716000000, P_DDRPLLAPSS, 1, 0, 0),

Didn't this patch series introduce table updates already? Why
can't this patch be squashed with that one?

>  	{ }

-- 
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