| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1478101374-18778-2-git-send-email-anurup.m@huawei.com>
Date: Wed, 2 Nov 2016 11:42:44 -0400
From: Anurup M <anurupvasu@...il.com>
To: anurup.m@...wei.com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: will.deacon@....com, mark.rutland@....com,
zhangshaokun@...ilicon.com, xuwei5@...ilicon.com,
john.garry@...wei.com, gabriele.paoloni@...wei.com,
sanil.kumar@...ilicon.com, shyju.pv@...wei.com,
tanxiaojun@...wei.com, shiju.jose@...wei.com, linuxarm@...wei.com
Subject: [PATCH v1 01/11] arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
Add support for Hisilicon SoC hardware event counters
for HIP05/06/07 chip versions.
Signed-off-by: Anurup M <anurup.m@...wei.com>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b224caa..839abc8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5725,6 +5725,16 @@ S: Maintained
F: drivers/net/ethernet/hisilicon/
F: Documentation/devicetree/bindings/net/hisilicon*.txt
+HISILICON SOC PMU
+M: Anurup M <anurup.m@...wei.com>
+W: http://www.hisilicon.com
+S: Supported
+F: drivers/perf/hisilicon/*
+F: drivers/soc/hisilicon/djtag.c
+F: include/linux/soc/hisilicon/djtag.h
+F: Documentation/perf/hisi-pmu.txt
+F: Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
+
HISILICON ROCE DRIVER
M: Lijun Ou <oulijun@...wei.com>
M: Wei Hu(Xavier) <xavier.huwei@...wei.com>
--
2.1.4
Powered by blists - more mailing lists