linux-kernel - Re: [PATCHv2] PCI: QDF2432 32 bit config space accessors

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Message-ID: <20161102160820.GA6568@bhelgaas-glaptop.roam.corp.google.com>
Date:   Wed, 2 Nov 2016 11:08:20 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     cov@...eaurora.org
Cc:     Sinan Kaya <okaya@...eaurora.org>,
        Tomasz Nowicki <tn@...ihalf.com>, will.deacon@....com,
        catalin.marinas@....com, rafael@...nel.org,
        Lorenzo.Pieralisi@....com, arnd@...db.de, hanjun.guo@...aro.org,
        jchandra@...adcom.com, dhdang@....com, ard.biesheuvel@...aro.org,
        robert.richter@...iumnetworks.com, mw@...ihalf.com,
        Liviu.Dudau@....com, ddaney@...iumnetworks.com,
        wangyijing@...wei.com, msalter@...hat.com,
        linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linaro-acpi@...ts.linaro.org, jcm@...hat.com,
        andrea.gallo@...aro.org, jeremy.linton@....com,
        liudongdong3@...wei.com, gabriele.paoloni@...wei.com,
        jhugo@...eaurora.org, linux-acpi@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCHv2] PCI: QDF2432 32 bit config space accessors

On Tue, Nov 01, 2016 at 07:06:31AM -0600, cov@...eaurora.org wrote:
> Hi Bjorn,
> 
> On 2016-10-31 15:48, Bjorn Helgaas wrote:
> >On Wed, Sep 21, 2016 at 06:38:05PM -0400, Christopher Covington wrote:
> >>The Qualcomm Technologies QDF2432 SoC does not support accesses
> >>smaller
> >>than 32 bits to the PCI configuration space. Register the appropriate
> >>quirk.
> >>
> >>Signed-off-by: Christopher Covington <cov@...eaurora.org>
> >
> >Hi Christopher,
> >
> >Can you rebase this against v4.9-rc1?  It no longer applies to my tree.
> 
> I apologize for not being clearer. This patch depends on:
> 
> PCI/ACPI: Extend pci_mcfg_lookup() responsibilities
> PCI/ACPI: Check platform-specific ECAM quirks
> 
> These patches from Tomasz Nowicki were previously in your pci/ecam-v6
> branch, but that seems to have come and gone. How would you like to
> proceed?

Oh yes, that's right, I forgot that connection.  I'm afraid I kind of
dropped the ball on that thread, so I went back and read through it
again.

I *think* the current state is:

  - I'm OK with the first two patches that add the quirk
    infrastructure.

  - My issue with the last three patches that add ThunderX quirks is
    that there's no generic description of the ECAM address space.

So if I understand correctly, your Qualcomm patch depends only on the
first two patches.

Then the question is how the Qualcomm ECAM address space is described.
Your quirk overrides the default pci_generic_ecam_ops with the
&pci_32b_ops, but it doesn't touch the address space part, so I assume
the bus ranges and corresponding address space in your MCFG is
correct.  So far, so good.

Is there also an ACPI device that contains that space in _CRS?  I
think we concluded that the standard solution is to describe this with
a PNP0C02 device.

Would you mind opening a bugzilla at bugzilla.kernel.org and attaching
the dmesg log, /proc/iomem, and maybe a DSDT dump?  I'd like to have
something to point at to say "if you need an MCFG quirk, you need the
MCFG bit and *also* these other related ACPI device bits, and here's
how it should be done."

Bjorn