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Message-ID: <fb7b486b-aa2a-e2c2-cd41-c0ee934f9cf2@nvidia.com>
Date: Thu, 3 Nov 2016 13:45:39 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Mirza Krak <mirza.krak@...il.com>, <swarren@...dotorg.org>,
<thierry.reding@...il.com>
CC: <gnurou@...il.com>, <linux@...linux.org.uk>,
<pdeschrijver@...dia.com>, <pgaikwad@...dia.com>,
<mturquette@...libre.com>, <sboyd@...eaurora.org>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@...il.com>
>
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
>
> Signed-off-by: Mirza Krak <mirza.krak@...il.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh@...dia.com>
Cheers
Jon
--
nvpublic
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