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Date:   Thu, 3 Nov 2016 23:35:23 +0100
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Vineet Gupta <Vineet.Gupta1@...opsys.com>
Cc:     Noam Camus <noamca@...lanox.com>, tglx@...utronix.de,
        linux-snps-arc@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Alexey.Brodkin@...opsys.com, stable@...r.kernel.org
Subject: Re: [PATCH v2 01/10] ARC: timer: rtc: implement read loop in "C" vs.
 inline asm

On Thu, Nov 03, 2016 at 03:23:09PM -0700, Vineet Gupta wrote:
> On 11/03/2016 02:52 PM, Daniel Lezcano wrote:
> > On Thu, Nov 03, 2016 at 02:31:32PM -0700, Vineet Gupta wrote:
> >> The current code doesn't even compile ....
> > 
> > Give a better description in the log, especially if this patch is supposed to
> > go to stable@
> 
> OK.

[ ... ]

> > Is the condition correct ? If I refer to your previous answer, the bit will be
> > set for status if the counter wrapped up. So in this case, we won't exit the
> > loop until we wrap up, no ?
> 
> No thats not what I meant. Bit being set there means things are fine (no interrupt
> taken, no increment of high after low was readetc). All I changed here was use of
> 0x8000_0000 to the macro. BBIT0 in assembler means branch if bit was clear.

Fair enough. So the logic is inverted 'status' == 0 means 'not fine'.

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