linux-kernel - Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK

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Date:   Mon, 7 Nov 2016 12:27:53 +0100
From:   Thierry Reding <thierry.reding@...il.com>
To:     Mirza Krak <mirza.krak@...il.com>
Cc:     swarren@...dotorg.org, jonathanh@...dia.com, gnurou@...il.com,
        linux@...linux.org.uk, pdeschrijver@...dia.com,
        pgaikwad@...dia.com, mturquette@...libre.com, sboyd@...eaurora.org,
        robh+dt@...nel.org, mark.rutland@....com,
        devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org
Subject: Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

On Mon, Nov 07, 2016 at 09:30:00AM +0100, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@...il.com>
> 
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
> 
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
> 
> Signed-off-by: Mirza Krak <mirza.krak@...il.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <jonathanh@...dia.com>
> ---
> 
> Changes in v2:
> - no changes
> 
> Changes in v3:
> - Added comment in commit message where I got the maximum rates from.
> 
> Changes in V4:
> - no changes

Applied, thanks.

Thierry

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