linux-kernel - Re: [PATCH v8 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 7 Nov 2016 18:53:39 +0100
From:   Marek Vasut <marex@...x.de>
To:     Joel Holdsworth <joel@...webreathe.org.uk>,
        atull@...nsource.altera.com, moritz.fischer@...us.com,
        geert@...ux-m68k.org, robh@...nel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
        clifford@...fford.at
Subject: Re: [PATCH v8 2/3] Documentation: Add binding document for Lattice
 iCE40 FPGA manager

On 11/07/2016 03:49 AM, Joel Holdsworth wrote:
> This adds documentation of the device tree bindings of the Lattice iCE40
> FPGA driver for the FPGA manager framework.
> 
> Signed-off-by: Joel Holdsworth <joel@...webreathe.org.uk>
> ---
>  .../bindings/fpga/lattice-ice40-fpga-mgr.txt        | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> 
> diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> new file mode 100644
> index 0000000..7e7a78b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> @@ -0,0 +1,21 @@
> +Lattice iCE40 FPGA Manager
> +
> +Required properties:
> +- compatible:		Should contain "lattice,ice40-fpga-mgr"
> +- reg:			SPI chip select
> +- spi-max-frequency:	Maximum SPI frequency (>=1000000, <=25000000)
> +- cdone-gpios:		GPIO input connected to CDONE pin
> +- reset-gpios:		Active-low GPIO output connected to CRESET_B pin. Note
> +			that unless the GPIO is held low during startup, the
> +			FPGA will enter Master SPI mode and drive SCK with a
> +			clock signal potentially jamming other devices on the
> +			bus until the firmware is loaded.
> +
> +Example:
> +	ice40: ice40@0 {
> +		compatible = "lattice,ice40-fpga-mgr";
> +		reg = <0>;
> +		spi-max-frequency = <1000000>;
> +		cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;

Wouldn't it make more sense to have "gpios" and "gpio-names" ? That
scales better imo, although in this case we cannot really talk about
scaling.

> +	};
> 


-- 
Best regards,
Marek Vasut