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Message-ID: <alpine.DEB.2.20.1611082002160.3501@nanos>
Date: Tue, 8 Nov 2016 20:06:28 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Kyle Huey <me@...ehuey.com>
cc: Robert O'Callahan <robert@...llahan.org>,
Andy Lutomirski <luto@...nel.org>,
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Subject: Re: [PATCH v10 5/7] x86/cpufeature: Detect CPUID faulting support
On Tue, 8 Nov 2016, Kyle Huey wrote:
> Intel supports faulting on the CPUID instruction beginning with Ivy Bridge.
> When enabled, the processor will fault on attempts to execute the CPUID
> instruction with CPL>0. This will allow a ptracer to emulate the CPUID
> instruction.
>
> Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
> documented in detail in Section 2.3.2 of
> http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf
Can you please stick that document into the kernel bugzilla, as it's going
to be on a different place before this gets merged into Linus tree?
See: http://lkml.kernel.org/r/1478631281-5061-1-git-send-email-kan.liang@intel.com
> + static const struct msr_bit msr_bits[] = {
> + { X86_FEATURE_CPUID_FAULT, MSR_PLATFORM_INFO, 31 },
Can you please make that PLATINFO_CPUID_FAULT_BIT instead of 31?
Thanks,
tglx
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