linux-kernel - [PATCH v2 8/9] arm64: dts: rockchip: support dwc3 USB for rk3399

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Message-Id: <1478697721-2323-9-git-send-email-wxt@rock-chips.com>
Date:   Wed,  9 Nov 2016 21:22:00 +0800
From:   Caesar Wang <wxt@...k-chips.com>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     eddie.cai@...k-chips.com, tfiga@...omium.org,
        Brian Norris <briannorris@...omium.org>,
        Caesar Wang <wxt@...k-chips.com>,
        Douglas Anderson <dianders@...omium.org>,
        David Wu <david.wu@...k-chips.com>,
        Jianqun Xu <jay.xu@...k-chips.com>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, zhangqing <zhangqing@...k-chips.com>,
        Shawn Lin <shawn.lin@...k-chips.com>,
        Rob Herring <robh+dt@...nel.org>,
        Will Deacon <will.deacon@....com>,
        linux-rockchip@...ts.infradead.org,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v2 8/9] arm64: dts: rockchip: support dwc3 USB for rk3399

From: Brian Norris <briannorris@...omium.org>

Add the dwc3 usb needed node information for rk3399.

Signed-off-by: Brian Norris <briannorris@...omium.org>
Signed-off-by: Caesar Wang <wxt@...k-chips.com>
---

Changes in v2:
- the original patches from brian posting on
  https://chromium-review.googlesource.com/343603

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 54 ++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 09ebf4e..3659c56 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -353,6 +353,60 @@
 		status = "disabled";
 	};
 
+	usbdrd3_0: usb@...00000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_0: dwc3@...00000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe800000 0x0 0x100000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "otg";
+			phys = <&tcphy0_usb3>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,xhci-slow-suspend-quirk;
+			status = "disabled";
+		};
+	};
+
+	usbdrd3_1: usb@...00000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_1: dwc3@...00000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe900000 0x0 0x100000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "host";
+			phys = <&tcphy1_usb3>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,xhci-slow-suspend-quirk;
+			status = "disabled";
+		};
+	};
+
 	gic: interrupt-controller@...00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <4>;
-- 
2.7.4