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Message-ID: <tip-b0b6e86846093c5f8820386bc01515f857dd8faa@git.kernel.org>
Date: Wed, 9 Nov 2016 08:13:45 -0800
From: tip-bot for Yazen Ghannam <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: hpa@...or.com, torvalds@...ux-foundation.org, bp@...e.de,
tglx@...utronix.de, peterz@...radead.org,
linux-kernel@...r.kernel.org, aravindksg.lkml@...il.com,
Yazen.Ghannam@....com, mingo@...nel.org
Subject: [tip:x86/urgent] x86/cpu/AMD: Fix cpu_llc_id for AMD Fam17h systems
Commit-ID: b0b6e86846093c5f8820386bc01515f857dd8faa
Gitweb: http://git.kernel.org/tip/b0b6e86846093c5f8820386bc01515f857dd8faa
Author: Yazen Ghannam <Yazen.Ghannam@....com>
AuthorDate: Tue, 8 Nov 2016 09:35:06 +0100
Committer: Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 9 Nov 2016 17:06:08 +0100
x86/cpu/AMD: Fix cpu_llc_id for AMD Fam17h systems
cpu_llc_id (Last Level Cache ID) derivation on AMD Fam17h has an
underflow bug when extracting the socket_id value. It starts from 0
so subtracting 1 from it will result in an invalid value. This breaks
scheduling topology later on since the cpu_llc_id will be incorrect.
For example, the the cpu_llc_id of the *other* CPU in the loops in
set_cpu_sibling_map() underflows and we're generating the funniest
thread_siblings masks and then when I run 8 threads of nbench, they get
spread around the LLC domains in a very strange pattern which doesn't
give you the normal scheduling spread one would expect for performance.
Other things like EDAC use cpu_llc_id so they will be b0rked too.
So, the APIC ID is preset in APICx020 for bits 3 and above: they contain
the core complex, node and socket IDs.
The LLC is at the core complex level so we can find a unique cpu_llc_id
by right shifting the APICID by 3 because then the least significant bit
will be the Core Complex ID.
Tested-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@....com>
[ Cleaned up and extended the commit message. ]
Signed-off-by: Borislav Petkov <bp@...e.de>
Acked-by: Thomas Gleixner <tglx@...utronix.de>
Cc: <stable@...r.kernel.org> # v4.4..
Cc: Aravind Gopalakrishnan <aravindksg.lkml@...il.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h systems")
Link: http://lkml.kernel.org/r/20161108083506.rvqb5h4chrcptj7d@pd.tnic
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/kernel/cpu/amd.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index b81fe2d..1e81a37 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -347,7 +347,6 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
#ifdef CONFIG_SMP
unsigned bits;
int cpu = smp_processor_id();
- unsigned int socket_id, core_complex_id;
bits = c->x86_coreid_bits;
/* Low order bits define the core id (index of core in socket) */
@@ -365,10 +364,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
return;
- socket_id = (c->apicid >> bits) - 1;
- core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3;
-
- per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
+ per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
#endif
}
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