linux-kernel - Re: [PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs

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Message-ID: <eece3eba-fd24-ad96-ca20-c08403894b00@gmail.com>
Date:   Wed, 9 Nov 2016 18:20:21 +0100
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Erin Lo <erin.lo@...iatek.com>,
        Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Rob Herring <robh@...nel.org>
Cc:     Arnd Bergmann <arnd@...db.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Daniel Kurtz <djkurtz@...omium.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        linux-clk@...r.kernel.org, srv_heupstream@...iatek.com,
        ms.chen@...iatek.com, robert.chou@...iatek.com
Subject: Re: [PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs



On 11/04/2016 08:43 AM, Erin Lo wrote:
> We used to use a fixed rate clock for the UARTs. Now that we have clock
> support we can associate the correct clocks to the UARTs and drop the
> 26MHz fixed rate UART clock.
>
> Signed-off-by: Erin Lo <erin.lo@...iatek.com>

Applied, thanks.

> ---
>  arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index c9a8dbf..7eab6f4 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -73,12 +73,6 @@
>  		#clock-cells = <0>;
>  	};
>
> -	uart_clk: dummy26m {
> -		compatible = "fixed-clock";
> -		clock-frequency = <26000000>;
> -		#clock-cells = <0>;
> -	};
> -
>  	clk26m: oscillator@0 {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> @@ -186,7 +180,8 @@
>  			     "mediatek,mt6577-uart";
>  		reg = <0 0x11002000 0 0x400>;
>  		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
> -		clocks = <&uart_clk>;
> +		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> +		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
>
> @@ -195,7 +190,8 @@
>  			     "mediatek,mt6577-uart";
>  		reg = <0 0x11003000 0 0x400>;
>  		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> -		clocks = <&uart_clk>;
> +		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> +		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
>
> @@ -204,7 +200,8 @@
>  			     "mediatek,mt6577-uart";
>  		reg = <0 0x11004000 0 0x400>;
>  		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
> -		clocks = <&uart_clk>;
> +		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> +		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
>
> @@ -213,7 +210,8 @@
>  			     "mediatek,mt6577-uart";
>  		reg = <0 0x11005000 0 0x400>;
>  		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
> -		clocks = <&uart_clk>;
> +		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> +		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
>  };
>