lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <f7917987-a4cb-2840-8128-07eebd242c17@denx.de>
Date:   Wed, 9 Nov 2016 13:01:56 +0100
From:   Marek Vasut <marex@...x.de>
To:     Joel Holdsworth <joel@...webreathe.org.uk>,
        Moritz Fischer <moritz.fischer@...us.com>
Cc:     Alan Tull <atull@...nsource.altera.com>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Rob Herring <robh@...nel.org>,
        Devicetree List <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-spi@...r.kernel.org, Clifford Wolf <clifford@...fford.at>
Subject: Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs

On 11/08/2016 06:30 PM, Joel Holdsworth wrote:
>>>> On the whole, I don't think the zero-length transfers are too
>>>> egregiously bad, and all the alternatives seem worse to me.
>>>
>>> So why not turn the CS line into GPIO and just toggle the GPIO?
>>
>> Does that work with *all* SPI controllers?
>>
> 
> It does not - no. See my other email.

And is that line an actual CS of that lattice chip or a generic input
which almost works like CS?

-- 
Best regards,
Marek Vasut

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ