linux-kernel - RE: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing

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Message-ID: <ED52C51D9B87F54892CE544909A13C6C1FF6ACF5@IRSMSX101.ger.corp.intel.com>
Date:   Wed, 9 Nov 2016 21:48:35 +0000
From:   "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@...el.com>
To:     Thomas Gleixner <tglx@...utronix.de>
CC:     "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>, "x86@...nel.org" <x86@...nel.org>,
        "bp@...e.de" <bp@...e.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "Daniluk, Lukasz" <lukasz.daniluk@...el.com>,
        "Cownie, James H" <james.h.cownie@...el.com>,
        "Pan, Jacob jun" <jacob.jun.pan@...el.com>,
        "Luc, Piotr" <Piotr.Luc@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for
 Knights Landing



-----Original Message-----
From: Thomas Gleixner [mailto:tglx@...utronix.de] 
Sent: Wednesday, November 9, 2016 3:32 PM
To: Andrejczuk, Grzegorz <grzegorz.andrejczuk@...el.com>
Cc: mingo@...hat.com; hpa@...or.com; x86@...nel.org; bp@...e.de; dave.hansen@...ux.intel.com; Daniluk, Lukasz <lukasz.daniluk@...el.com>; Cownie, James H <james.h.cownie@...el.com>; Pan, Jacob jun <jacob.jun.pan@...el.com>; Luc, Piotr <Piotr.Luc@...el.com>; linux-kernel@...r.kernel.org
Subject: Re: [PATCH v9 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing

On Wed, 9 Nov 2016, Grzegorz Andrejczuk wrote:

> These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT 
> instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs.
> Then expose it as CPU feature and introduces elf HWCAP capability for x86.
> Reference:
> https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-produ
> ct-family-x200-knl-user-mode-ring-3-monitor-and-mwait
> 
> v9:
> Removed PHI from defines
>
> Do I really have to spell out everything? I asked you several times to get rid of all PHI associations except for the feature detection logic.
>
> But no, you still insist on it being a PHI special feature and once it becomes available on other models, which can be expected, we can deal with the cleanup and a PHI specific kernel parameter which we have to support forever.
>
> I'm slowly starting to get really grumpy. Your attitude of just addressing review comments in the most minimal way w/o thinking about the big picture is annoying.
>
> This is hillarious. 9 versions of that simple thing, just because you insist on slapping PHI to everything despite being told otherwise.
>
> I do not care about the time you waste with this, but I very much care about the time you steal from me. 
>
> If you can't be bothered to send something which addresses _ALL_ my review comments, then so be it. The next version is the last one I'm going to look at.
>
> Thanks,
>
>	Tglx


Hi, 

Sorry we end up in this situation. 

I have removed PHI from:
- MSR definition,
- HWCAP2 bit,
- X86_CPU_FEATURE

Making kernel parameter non-phi would require implementing the ring3mwait=disable for any other non-ring 0 MWAIT (i.e AMD MWAITX). 
My concern is that kernel will have to maintain various non architectural model specific stuff in single kernel parameter. 

Best Regards,
Grzegorz