lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 9 Nov 2016 18:34:59 -0600 From: Tom Lendacky <thomas.lendacky@....com> To: <linux-arch@...r.kernel.org>, <linux-efi@...r.kernel.org>, <kvm@...r.kernel.org>, <linux-doc@...r.kernel.org>, <x86@...nel.org>, <linux-kernel@...r.kernel.org>, <kasan-dev@...glegroups.com>, <linux-mm@...ck.org>, <iommu@...ts.linux-foundation.org> CC: Rik van Riel <riel@...hat.com>, Radim Krčmář <rkrcmar@...hat.com>, Arnd Bergmann <arnd@...db.de>, Jonathan Corbet <corbet@....net>, Matt Fleming <matt@...eblueprint.co.uk>, Joerg Roedel <joro@...tes.org>, Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>, "Paolo Bonzini" <pbonzini@...hat.com>, Larry Woodman <lwoodman@...hat.com>, "Ingo Molnar" <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>, Andy Lutomirski <luto@...nel.org>, "H. Peter Anvin" <hpa@...or.com>, Andrey Ryabinin <aryabinin@...tuozzo.com>, Alexander Potapenko <glider@...gle.com>, "Thomas Gleixner" <tglx@...utronix.de>, Dmitry Vyukov <dvyukov@...gle.com> Subject: [RFC PATCH v3 03/20] x86: Add the Secure Memory Encryption cpu feature Update the cpu features to include identifying and reporting on the Secure Memory Encryption feature. Signed-off-by: Tom Lendacky <thomas.lendacky@....com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b212b86..f083ea1 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -187,6 +187,7 @@ * Reuse free bits when adding new feature flags! */ +#define X86_FEATURE_SME ( 7*32+ 0) /* AMD Secure Memory Encryption */ #define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */ #define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 8cb57df..d86d9a5 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -37,6 +37,7 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 }, + { X86_FEATURE_SME, CR_EAX, 0, 0x8000001f, 0 }, { 0, 0, 0, 0, 0 } };
Powered by blists - more mailing lists