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Message-ID: <20161122175243.8853-6-Zubair.Kakakhel@imgtec.com>
Date: Tue, 22 Nov 2016 17:52:42 +0000
From: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@...tec.com>
To: <ralf@...ux-mips.org>
CC: <Zubair.Kakakhel@...tec.com>, <linux-mips@...ux-mips.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH 5/6] MIPS: xilfpga: Add DT node for AXI emaclite
The xilfpga platform has a Xilinx AXI emaclite block.
Add the DT node to use it.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@...tec.com>
---
arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index f5ebab8..09a62f2 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
@@ -42,6 +42,32 @@
xlnx,tri-default = <0xffffffff>;
} ;
+ axi_ethernetlite: ethernet@...00000 {
+ compatible = "xlnx,xps-ethernetlite-3.00.a";
+ device_type = "network";
+ interrupt-parent = <&axi_intc>;
+ interrupts = <1>;
+ phy-handle = <&phy0>;
+ reg = <0x10e00000 0x10000>;
+ xlnx,duplex = <0x1>;
+ xlnx,include-global-buffers = <0x1>;
+ xlnx,include-internal-loopback = <0x0>;
+ xlnx,include-mdio = <0x1>;
+ xlnx,instance = "axi_ethernetlite_inst";
+ xlnx,rx-ping-pong = <0x1>;
+ xlnx,s-axi-id-width = <0x1>;
+ xlnx,tx-ping-pong = <0x1>;
+ xlnx,use-internal = <0x0>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@1 {
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
+
axi_uart16550: serial@...00000 {
compatible = "ns16550a";
reg = <0x10400000 0x10000>;
--
2.10.2
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