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Message-ID: <ecd1bbe1-70b8-32d3-e5a3-41af835bceba@redhat.com>
Date: Tue, 22 Nov 2016 23:29:56 +0100
From: Paolo Bonzini <pbonzini@...hat.com>
To: Tom Lendacky <thomas.lendacky@....com>,
Brijesh Singh <brijesh.singh@....com>, kvm@...r.kernel.org
Cc: rkrcmar@...hat.com, joro@...tes.org, x86@...nel.org,
linux-kernel@...r.kernel.org, mingo@...hat.com, hpa@...or.com,
tglx@...utronix.de, bp@...e.de
Subject: Re: [PATCH v1 1/3] kvm: svm: Add support for additional SVM NPF error
codes
On 22/11/2016 23:15, Tom Lendacky wrote:
> > 2) what bit is set if the processor is reading the PDPTEs of a 32-bit
> > PAE guest?
>
> I believe that bit 33 will be set. The PDPE's are considered guest
> tables and are read during a guest table walk (see APM vol2 section
> 15.25.10). Note that this is slightly different than the bare-metal
> behavior of legacy PAE mode as APM describes. I'll try to test this
> and verify it.
No big deal, indeed it's a bit different from Intel which caches the
four PDPEs, but it's enough to know that bit 33 will be set.
Paolo
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