linux-kernel - [PATCH 9/9] ARM: dts: rockchip: add timer entries to rk3188.dtsi

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1479922177-20136-9-git-send-email-al.kochet@gmail.com>
Date:   Wed, 23 Nov 2016 20:29:37 +0300
From:   Alexander Kochetkov <al.kochet@...il.com>
To:     daniel.lezcano@...aro.org, tglx@...utronix.de, heiko@...ech.de,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org
Cc:     Alexander Kochetkov <al.kochet@...il.com>
Subject: [PATCH 9/9] ARM: dts: rockchip: add timer entries to rk3188.dtsi

This is correct configuration borrowed from 3.0 kernel[1].
timer 6 used as clocksource, timers 0, 1, 4 and 5 used
as clockevents.

Timers can do interrupts and work as expected with correct
driver support.

[1] https://github.com/radxa/linux-rockchip/blob/radxa-stable-3.0/arch/arm/mach-rk3188/rk_timer.c

Signed-off-by: Alexander Kochetkov <al.kochet@...il.com>
---
 arch/arm/boot/dts/rk3188.dtsi |   45 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 31f81b2..e2f88c8 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -106,6 +106,51 @@
 		};
 	};
 
+	timer0: timer@...38000 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x20038000 0x20>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
+		clock-names = "timer", "pclk";
+		status = "disabled";
+	};
+
+	timer1: timer@...38020 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x20038020 0x20>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER0>;
+		clock-names = "timer", "pclk";
+		status = "disabled";
+	};
+
+	timer4: timer@...38060 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x20038060 0x20>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TIMER4>, <&cru PCLK_TIMER0>;
+		clock-names = "timer", "pclk";
+		status = "disabled";
+	};
+
+	timer5: timer@...38080 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x20038080 0x20>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TIMER5>, <&cru PCLK_TIMER0>;
+		clock-names = "timer", "pclk";
+		status = "disabled";
+	};
+
+	timer6: timer@...380A0 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x200380A0 0x20>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
+		clock-names = "timer", "pclk";
+		status = "disabled";
+	};
+
 	i2s0: i2s@...1a000 {
 		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
 		reg = <0x1011a000 0x2000>;
-- 
1.7.9.5