linux-kernel - Re: Tearing down DMA transfer setup after DMA client has finished

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Message-ID: <ae97a212-a91e-5e0a-c9b6-2dba3b79ddc5@free.fr>
Date:   Fri, 25 Nov 2016 15:05:05 +0100
From:   Mason <slash.tmp@...e.fr>
To:     Mans Rullgard <mans@...sr.com>, Vinod Koul <vinod.koul@...el.com>
Cc:     dmaengine@...r.kernel.org,
        Linus Walleij <linus.walleij@...aro.org>,
        Dan Williams <dan.j.williams@...el.com>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Jon Mason <jdmason@...zu.us>, Mark Brown <broonie@...nel.org>,
        Lars-Peter Clausen <lars@...afoo.de>,
        Lee Jones <lee.jones@...aro.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        Arnd Bergmann <arnd@...db.de>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Dave Jiang <dave.jiang@...el.com>,
        Peter Ujfalusi <peter.ujfalusi@...com>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: Tearing down DMA transfer setup after DMA client has finished

On 25/11/2016 12:57, Måns Rullgård wrote:

> The same DMA unit is also used for SATA, which is an off the shelf
> Designware controller with an in-kernel driver.  This interrupt timing
> glitch can actually explain some intermittent errors I've observed with
> it.

FWIW, newer chips embed an AHCI controller, with a dedicated
memory channel.

FWIW2, the HW dev said memory channels are "almost free", and he
would have no problem giving each device their own private channel
read/write pair.

Regards.