[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <yw1xwpfr7h9y.fsf@unicorn.mansr.com>
Date: Fri, 25 Nov 2016 14:42:17 +0000
From: Måns Rullgård <mans@...sr.com>
To: Mason <slash.tmp@...e.fr>
Cc: Vinod Koul <vinod.koul@...el.com>, dmaengine@...r.kernel.org,
Linus Walleij <linus.walleij@...aro.org>,
Dan Williams <dan.j.williams@...el.com>,
LKML <linux-kernel@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Jon Mason <jdmason@...zu.us>, Mark Brown <broonie@...nel.org>,
Lars-Peter Clausen <lars@...afoo.de>,
Lee Jones <lee.jones@...aro.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Arnd Bergmann <arnd@...db.de>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Dave Jiang <dave.jiang@...el.com>,
Peter Ujfalusi <peter.ujfalusi@...com>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>
Subject: Re: Tearing down DMA transfer setup after DMA client has finished
Mason <slash.tmp@...e.fr> writes:
> On 25/11/2016 15:12, Måns Rullgård wrote:
>
>> Mason writes:
>>
>>> On 25/11/2016 12:57, Måns Rullgård wrote:
>>>
>>>> The same DMA unit is also used for SATA, which is an off the shelf
>>>> Designware controller with an in-kernel driver. This interrupt timing
>>>> glitch can actually explain some intermittent errors I've observed with
>>>> it.
>>>
>>> FWIW, newer chips embed an AHCI controller, with a dedicated
>>> memory channel.
>>>
>>> FWIW2, the HW dev said memory channels are "almost free", and he
>>> would have no problem giving each device their own private channel
>>> read/write pair.
>>
>> We still need to deal with the existing hardware.
>
> Can you confirm that your MBUS driver, in its current form,
> does not support memcpy-type transfers, which generate two
> IRQs (one from send agent, one from receive agent)?
It does not.
> Do you plan to support that, or is it just too quirky?
I hadn't planned on doing that, but I'm ruling it out entirely.
--
Måns Rullgård
Powered by blists - more mailing lists