linux-kernel - Re: [PATCH] perf/x86: fix event counter update issue

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Message-ID: <20161129171715.GO3092@twins.programming.kicks-ass.net>
Date:   Tue, 29 Nov 2016 18:17:15 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     "Liang, Kan" <kan.liang@...el.com>
Cc:     "mingo@...hat.com" <mingo@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "eranian@...gle.com" <eranian@...gle.com>,
        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>,
        "Odzioba, Lukasz" <lukasz.odzioba@...el.com>
Subject: Re: [PATCH] perf/x86: fix event counter update issue

On Tue, Nov 29, 2016 at 05:06:36PM +0000, Liang, Kan wrote:
> 
> 
> > On Tue, Nov 29, 2016 at 02:46:14PM +0000, Liang, Kan wrote:
> > > > And note that we _ALWAYS_ set the IN bits, even for !sampling events.
> > > > Also note we set max_period to (1<<31) - 1, so we should never
> > > > exceed 31 bits.
> > > >
> > >
> > > The max_period is 0xfffffffff.
> > >
> > > The limit is breaked by this patch.
> > > 069e0c3c4058 ("perf/x86/intel: Support full width counting")
> > > https://patchwork.kernel.org/patch/2784191/
> > >
> > > 	/* Support full width counters using alternative MSR range */
> > > 	if (x86_pmu.intel_cap.full_width_write) {
> > > 		x86_pmu.max_period = x86_pmu.cntval_mask;
> > > 		x86_pmu.perfctr = MSR_IA32_PMC0;
> > > 		pr_cont("full-width counters, ");
> > > 	}
> > >
> > 
> > Wth do KNL/SLM have full_width_write set if they have short counters?
> 
> Yes, the full_width_write is set on KNL/SLM.
> 
> > I should the whole point of the full_wdith thing was that in that case the
> > counters were actually 64bit wide.
> 
> Even for big core, the counter width is 48 bit.
> AFAIK, no Intel platform has 64bit wide counter.

Then yes, that patch is very broken.