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Message-ID: <20161208231444.GX5423@codeaurora.org>
Date:   Thu, 8 Dec 2016 15:14:44 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Christophe JAILLET <christophe.jaillet@...adoo.fr>
Cc:     mturquette@...libre.com, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, kernel-janitors@...r.kernel.org
Subject: Re: [PATCH] clk: cdce925: Fix limit check

On 11/11, Christophe JAILLET wrote:
> It is likely that instead of '1>64', 'q>64' was expected.
> 
> Moreover, according to datasheet,
>    http://www.ti.com/lit/ds/symlink/cdce925.pdf
>    SCAS847I - JULY 2007 - REVISED OCTOBER 2016
> PLL settings limits are: 16 <= q <= 63
> So change the upper limit check from 64 to 63.
> 
> Signed-off-by: Christophe JAILLET <christophe.jaillet@...adoo.fr>
> ---

Applied to clk-next

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