linux-kernel - Re: [RFC, PATCHv1 00/28] 5-level paging

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Message-ID: <20161209105120.GA3705@e104818-lin.cambridge.arm.com>
Date:   Fri, 9 Dec 2016 10:51:20 +0000
From:   Catalin Marinas <catalin.marinas@....com>
To:     Arnd Bergmann <arnd@...db.de>
Cc:     Ingo Molnar <mingo@...nel.org>,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Andrew Morton <akpm@...ux-foundation.org>, x86@...nel.org,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>, Andi Kleen <ak@...ux.intel.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Andy Lutomirski <luto@...capital.net>,
        linux-arch@...r.kernel.org, linux-mm@...ck.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        maxim.kuvyrkov@...aro.org, Will Deacon <will.deacon@....com>,
        broonie@...nel.org, schwidefsky@...ibm.com
Subject: Re: [RFC, PATCHv1 00/28] 5-level paging

On Fri, Dec 09, 2016 at 11:24:12AM +0100, Arnd Bergmann wrote:
> On Friday, December 9, 2016 6:01:30 AM CET Ingo Molnar wrote:
> > >   - Handle opt-in wider address space for userspace.
> > > 
> > >     Not all userspace is ready to handle addresses wider than current
> > >     47-bits. At least some JIT compiler make use of upper bits to encode
> > >     their info.
> > > 
> > >     We need to have an interface to opt-in wider addresses from userspace
> > >     to avoid regressions.
> > > 
> > >     For now, I've included testing-only patch which bumps TASK_SIZE to
> > >     56-bits. This can be handy for testing to see what breaks if we max-out
> > >     size of virtual address space.
> > 
> > So this is just a detail - but it sounds a bit limiting to me to provide an 'opt 
> > in' flag for something that will work just fine on the vast majority of 64-bit 
> > software.
> > 
> > Please make this an opt out compatibility flag instead: similar to how we handle 
> > address space layout limitations/quirks ABI details, such as ADDR_LIMIT_32BIT, 
> > ADDR_LIMIT_3GB, ADDR_COMPAT_LAYOUT, READ_IMPLIES_EXEC, etc.
> 
> We've had a similar discussion about JIT software on ARM64, which has a wide
> range of supported page table layouts and some software wants to limit that
> to a specific number.
> 
> I don't remember the outcome of that discussion, but I'm adding a few people
> to Cc that might remember.

The arm64 kernel supports several user VA space configurations (though
commonly 39 and 48-bit) and has had these from the initial port. We
realised that certain JITs (e.g.
https://bugzilla.mozilla.org/show_bug.cgi?id=1143022) and IIRC LLVM
assume a 47-bit user VA but AFAICT, most have been fixed.

ARMv8.1 also supports 52-bit VA (though only with 64K pages and we
haven't added support for it yet). However, it's likely that if we make
a 52-bit TASK_SIZE this the default, we will break some user
assumptions. While arguably that's not necessarily ABI, if user relies
on a 47 or 48-bit VA the kernel shouldn't break it. So I'm strongly
inclined to make the 52-bit TASK_SIZE an opt-in on arm64.

-- 
Catalin