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Message-ID: <1F3AC3675D538145B1661F571FE1805F2F3B77FA@irsmsx105.ger.corp.intel.com>
Date:   Fri, 9 Dec 2016 18:09:03 +0000
From:   "Tirdea, Irina" <irina.tirdea@...el.com>
To:     Stephen Boyd <sboyd@...eaurora.org>
CC:     "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "platform-driver-x86@...r.kernel.org" 
        <platform-driver-x86@...r.kernel.org>,
        Darren Hart <dvhart@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Michael Turquette <mturquette@...libre.com>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
        Mark Brown <broonie@...nel.org>, Takashi Iwai <tiwai@...e.com>,
        "Bossart, Pierre-louis" <pierre-louis.bossart@...el.com>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Len Brown <lenb@...nel.org>,
        "linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Pierre-Louis Bossart" <pierre-louis.bossart@...ux.intel.com>
Subject: RE: [PATCH v5 2/2] clk: x86: Add Atom PMC platform clocks

On 2016-12-09 02:25, Stephen Boyd wrote:
> On 12/07, Irina Tirdea wrote:
>> The BayTrail and CherryTrail platforms provide platform clocks
>> through their Power Management Controller (PMC).
>> 
>> The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0]) with a
>> frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
>> an a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
>> are available for general system use, where appropriate, and each
>> have Control & Frequency register fields associated with them.
>> 
>> For example, the usage for platform clocks suggested in the datasheet
>> is the following:
>>   PLT_CLK[2:0] - Camera
>>   PLT_CLK[3] - Audio Codec
>>   PLT_CLK[4] -
>>   PLT_CLK[5] - COMMs
>> Signed-off-by: Irina Tirdea <irina.tirdea@...el.com> Signed-off-by:
>> Pierre-Louis Bossart <pierre- louis.bossart@...ux.intel.com> ---
>>  drivers/clk/x86/Makefile                      |   1 +
>>  drivers/clk/x86/clk-byt-plt.c                 | 380
> ++++++++++++++++++++++++++
> 
> Is it possible to split the clk part from the platform part? I'd
> like to merge just the clk part if possible into the clk tree.
>

It would be great to have the clk part merged. I'll put the code in a
separate patch.

Thanks,
Irina

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