linux-kernel - Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

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Message-ID: <20161213225430.GN30845@gate.crashing.org>
Date:   Tue, 13 Dec 2016 16:54:30 -0600
From:   Segher Boessenkool <segher@...nel.crashing.org>
To:     christophe leroy <christophe.leroy@....fr>
Cc:     Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        Scott Wood <oss@...error.net>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs

On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote:
> Le 13/12/2016 à 20:15, Segher Boessenkool a écrit :
> >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
> >>At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
> >>set to mark the interrupt as recoverable.
> >>
> >>MSR RI has to be unset before writing into SRR0 and SRR1 at exception
> >>epilogs.
> >
> >Why?  What goes wrong without this?  Etc.
> 
> The following patch implements perf instruction counting using the 8xx 
> debug counters. When the counter reaches 0, it fires a debug exception.
> If that exception happens between the setting of srr0/srr1 and the rfi, 
> values set to srr0/srr1 are lost and we end up with an Oops.
> 
> To avoid that, MSR RI has to be unset. That way, because the debug 
> counters mode is set to masked mode in register LCTRL2, no debug 
> interrupt will happen during that critical phase.

Okay, so why then do you do an expensive sequence on all other processors?


Segher