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Message-ID: <20161214092103.xgs62aqkjgsseuqe@lukather>
Date:   Wed, 14 Dec 2016 10:21:03 +0100
From:   Maxime Ripard <maxime.ripard@...e-electrons.com>
To:     Icenowy Zheng <icenowy@...c.xyz>
Cc:     Russell King <linux@...linux.org.uk>, Chen-Yu Tsai <wens@...e.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Jorik Jonker <jorik@...pendief.biz>,
        Hans de Goede <hdegoede@...hat.com>,
        Quentin Schulz <quentin.schulz@...e-electrons.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin
 CPUX clock on A33

On Wed, Dec 14, 2016 at 04:54:14AM +0800, Icenowy Zheng wrote:
> 
> 
> 13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@...e-electrons.com>:
> > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
> >>  The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
> >>  be changeable by changing the rate of PLL_CPUX.
> >>
> >>  Add CLK_SET_RATE_PARENT flag to this clock.
> >>
> >>  Signed-off-by: Icenowy Zheng <icenowy@...c.xyz>
> >
> > Acked-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> 
> Excuse me, have you merged this patch?

Yes, sorry, that's what I meant :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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