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Message-Id: <1481710301-1454-2-git-send-email-zhengxing@rock-chips.com>
Date:   Wed, 14 Dec 2016 18:11:39 +0800
From:   Xing Zheng <zhengxing@...k-chips.com>
To:     linux-rockchip@...ts.infradead.org
Cc:     dianders@...gle.com, heiko@...ech.de,
        Xing Zheng <zhengxing@...k-chips.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Lin Huang <hl@...k-chips.com>,
        Chris Zhong <zyw@...k-chips.com>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs

This patch add two clock IDs for the usb phy 480m source clocks.

Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
---

 include/dt-bindings/clock/rk3399-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 220a60f..224daf7 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -132,6 +132,8 @@
 #define SCLK_RMII_SRC			166
 #define SCLK_PCIEPHY_REF100M		167
 #define SCLK_DDRC			168
+#define SCLK_USBPHY0_480M_SRC		169
+#define SCLK_USBPHY1_480M_SRC		170
 
 #define DCLK_VOP0			180
 #define DCLK_VOP1			181
-- 
2.7.4


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