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Message-ID: <CAD=FV=WTS5C1voL5UDwR7xUb5+rJwHOuE3KnqAiQPa_f9AeRFw@mail.gmail.com>
Date: Wed, 14 Dec 2016 16:27:49 -0800
From: Doug Anderson <dianders@...gle.com>
To: Xing Zheng <zhengxing@...k-chips.com>
Cc: "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
Heiko Stübner <heiko@...ech.de>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Lin Huang <hl@...k-chips.com>,
Chris Zhong <zyw@...k-chips.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs
Hi,
On Wed, Dec 14, 2016 at 2:11 AM, Xing Zheng <zhengxing@...k-chips.com> wrote:
> This patch add two clock IDs for the usb phy 480m source clocks.
>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>
> ---
>
> include/dt-bindings/clock/rk3399-cru.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
> index 220a60f..224daf7 100644
> --- a/include/dt-bindings/clock/rk3399-cru.h
> +++ b/include/dt-bindings/clock/rk3399-cru.h
> @@ -132,6 +132,8 @@
> #define SCLK_RMII_SRC 166
> #define SCLK_PCIEPHY_REF100M 167
> #define SCLK_DDRC 168
> +#define SCLK_USBPHY0_480M_SRC 169
> +#define SCLK_USBPHY1_480M_SRC 170
As mentioned in the dts patch, I don't think you need these since I'm
under the impression that nobody gets this clock. I think the USB
Controller get the ungated version of this clock.
-Doug
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