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Message-ID: <alpine.DEB.2.20.1612212122060.3424@nanos>
Date: Wed, 21 Dec 2016 21:23:40 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
cc: mingo@...hat.com, hpa@...or.com, x86@...nel.org,
linux-kernel@...r.kernel.org, Piotr.Luc@...el.com,
dave.hansen@...ux.intel.com
Subject: Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and
RING3MWAIT bit
On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
> #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
> #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
>
> +/* MISC_FEATURE_ENABLES non-architectural features */
> +#define MSR_MISC_FEATURE_ENABLES 0x00000140
> +
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
> +
This last define is not used anywhere. I told you before, but addressing my
review comments completely is an unduly burden, or what?
Thanks,
tglx
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