linux-kernel - [PATCH v2 1/8] PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433

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Message-id: <1482926212-19223-2-git-send-email-cw00.choi@samsung.com>
Date:   Wed, 28 Dec 2016 20:56:45 +0900
From:   Chanwoo Choi <cw00.choi@...sung.com>
To:     myungjoo.ham@...sung.com, kyungmin.park@...sung.com
Cc:     chanwoo@...nel.org, rjw@...ysocki.net, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Chanwoo Choi <cw00.choi@...sung.com>,
        Rob Herring <robh+dt@...nel.org>,
        Kukjin Kim <kgene@...nel.org>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Javier Martinez Canillas <javier@....samsung.com>,
        linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org
Subject: [PATCH v2 1/8] PM / devfreq: exynos-bus: Add the detailed correlation
 for Exynos5433

This patch adds the detailed corrleation between sub-blocks and VDD_INT power
line for Exynos5433. VDD_INT provided the power source to INT (Internal) block.

Cc: Rob Herring <robh+dt@...nel.org>
Cc: Kukjin Kim <kgene@...nel.org>
Cc: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Javier Martinez Canillas <javier@....samsung.com>
Cc: linux-samsung-soc@...r.kernel.org
Cc: devicetree@...r.kernel.org
Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
---
 Documentation/devicetree/bindings/devfreq/exynos-bus.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index d3ec8e676b6b..d085ef90d27c 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
 		|--- FSYS
 		|--- FSYS2
 
+- In case of Exynos5433, there is VDD_INT power line as following:
+	VDD_INT |--- G2D (parent device)
+		|--- MSCL
+		|--- GSCL
+		|--- JPEG
+		|--- MFC
+		|--- HEVC
+		|--- BUS0
+		|--- BUS1
+		|--- BUS2
+		|--- PERIS (Fixed clock rate)
+		|--- PERIC (Fixed clock rate)
+		|--- FSYS  (Fixed clock rate)
+
 Example1:
 	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
 	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-- 
1.9.1