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Date: Mon, 2 Jan 2017 01:51:17 -0500
From: Anurup M <anurupvasu@...il.com>
To: mark.rutland@....com, will.deacon@....com, robh+dt@...nel.org,
xuwei5@...ilicon.com, catalin.marinas@....com
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, anurup.m@...wei.com,
zhangshaokun@...ilicon.com, tanxiaojun@...wei.com,
sanil.kumar@...ilicon.com, john.garry@...wei.com,
gabriele.paoloni@...wei.com, shiju.jose@...wei.com,
linuxarm@...wei.com, shyju.pv@...wei.com, anurupvasu@...il.com
Subject: [PATCH v3 10/10] dts: arm64: hip06: Add Hisilicon SoC PMU support
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
Signed-off-by: Shaokun Zhang <zhangshaokun@...ilicon.com>
Signed-off-by: John Garry <john.garry@...wei.com>
Signed-off-by: Anurup M <anurup.m@...wei.com>
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 72 ++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index e861698..02ff95f 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -963,6 +963,78 @@
status = "disabled";
};
+ djtag0: djtag@...10000 {
+ compatible = "hisilicon,hip06-djtag-v1";
+ reg = <0x0 0x60010000 0x0 0x10000>;
+ hisi-scl-id = <0x02>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#2 */
+ pmul3c0 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x02>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#2 */
+ pmul3c1 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x04>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#2 */
+ pmul3c2 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#2 */
+ pmul3c3 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x08>;
+ };
+
+ /* Miscellaneous node for socket0 CPU die scl#2 */
+ pmumn0 {
+ compatible = "hisilicon,hip06-pmu-mn-v1";
+ hisi-module-id = <0x0b>;
+ };
+ };
+
+ djtag1: djtag@...10000 {
+ compatible = "hisilicon,hip06-djtag-v1";
+ reg = <0x0 0x40010000 0x0 0x10000>;
+ hisi-scl-id = <0x01>;
+
+ /* L3 cache bank 0 for socket0 CPU die scl#1 */
+ pmul3c0 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x02>;
+ };
+
+ /* L3 cache bank 1 for socket0 CPU die scl#1 */
+ pmul3c1 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x04>;
+ };
+
+ /* L3 cache bank 2 for socket0 CPU die scl#1 */
+ pmul3c2 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x01>;
+ };
+
+ /* L3 cache bank 3 for socket0 CPU die scl#1 */
+ pmul3c3 {
+ compatible = "hisilicon,hip06-pmu-l3c-v1";
+ hisi-module-id = <0x04 0x08>;
+ };
+
+ /* Miscellaneous node for socket0 CPU die scl#1 */
+ pmumn1 {
+ compatible = "hisilicon,hip06-pmu-mn-v1";
+ hisi-module-id = <0x0b>;
+ };
+ };
+
sas1: sas@...00000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
--
2.1.4
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