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Message-id: <20170104123435.30740-2-jh80.chung@samsung.com>
Date:   Wed, 04 Jan 2017 21:34:31 +0900
From:   Jaehoon Chung <jh80.chung@...sung.com>
To:     linux-pci@...r.kernel.org
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-samsung-soc@...r.kernel.org, bhelgaas@...gle.com,
        robh+dt@...nel.org, mark.rutland@....com, kgene@...nel.org,
        krzk@...nel.org, kishon@...com, jingoohan1@...il.com,
        vivek.gautam@...eaurora.org, pankaj.dubey@...sung.com,
        alim.akhtar@...sung.com, cpgs@...sung.com,
        Jaehoon Chung <jh80.chung@...sung.com>
Subject: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy
 binding

Adds the exynos-pcie-phy binding for Exynos PCIe PHY.
This is for using generic PHY framework.

Signed-off-by: Jaehoon Chung <jh80.chung@...sung.com>
---
Changelog on V2:
- Remove the child node.
- Add 2nd address to the parent reg prop.

 Documentation/devicetree/bindings/phy/samsung-phy.txt | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 9872ba8..ab80bfe 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,3 +191,20 @@ Example:
 		usbdrdphy0 = &usb3_phy0;
 		usbdrdphy1 = &usb3_phy1;
 	};
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+	- First is for phy register, second is for block register.
+- reg-names : Must be set to "phy" and "block".
+
+Example:
+	pcie_phy0: pcie-phy@...000 {
+		#phy-cells = <0>;
+		compatible = "samsung,exynos5440-pcie-phy";
+		reg = <0x270000 0x1000>, <0x271000 0x40>;
+		reg-names = "phy", "block";
+	};
-- 
2.10.2

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