linux-kernel - Re: [PATCH RFC 0/4] 5-level EPT

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Message-ID: <20170105132658.GD17319@node.shutemov.name>
Date:   Thu, 5 Jan 2017 16:26:58 +0300
From:   "Kirill A. Shutemov" <kirill@...temov.name>
To:     Liang Li <liang.z.li@...el.com>
Cc:     kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, mingo@...hat.com,
        kirill.shutemov@...ux.intel.com, dave.hansen@...ux.intel.com,
        guangrong.xiao@...ux.intel.com, pbonzini@...hat.com,
        rkrcmar@...hat.com
Subject: Re: [PATCH RFC 0/4] 5-level EPT

On Thu, Dec 29, 2016 at 05:25:59PM +0800, Liang Li wrote:
> x86-64 is currently limited physical address width to 46 bits, which
> can support 64 TiB of memory. Some vendors require to support more for
> some use case. Intel plans to extend the physical address width to
> 52 bits in some of the future products.  
> 
> The current EPT implementation only supports 4 level page table, which
> can support maximum 48 bits physical address width, so it's needed to
> extend the EPT to 5 level to support 52 bits physical address width.
> 
> This patchset has been tested in the SIMICS environment for 5 level
> paging guest, which was patched with Kirill's patchset for enabling
> 5 level page table, with both the EPT and shadow page support. I just
> covered the booting process, the guest can boot successfully. 
> 
> Some parts of this patchset can be improved. Any comments on the design
> or the patches would be appreciated.

This looks reasonable, assuming my very limited knowledge of the subject.

The first patch is actually in my patchset, split across two patches.

-- 
 Kirill A. Shutemov