linux-kernel - [tip:x86/urgent] x86/cpu: Fix typo in the comment for Anniedale

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Message-ID: <tip-754c73cf4d2463022b2c9ae208026bf22564ed06@git.kernel.org>
Date:   Thu, 5 Jan 2017 07:05:56 -0800
From:   tip-bot for Andy Shevchenko <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mingo@...nel.org, peterz@...radead.org,
        torvalds@...ux-foundation.org, andriy.shevchenko@...ux.intel.com,
        hpa@...or.com, linux-kernel@...r.kernel.org, tglx@...utronix.de,
        dave.hansen@...ux.intel.com
Subject: [tip:x86/urgent] x86/cpu: Fix typo in the comment for Anniedale

Commit-ID:  754c73cf4d2463022b2c9ae208026bf22564ed06
Gitweb:     http://git.kernel.org/tip/754c73cf4d2463022b2c9ae208026bf22564ed06
Author:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
AuthorDate: Mon, 2 Jan 2017 11:22:29 +0200
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 5 Jan 2017 09:03:29 +0100

x86/cpu: Fix typo in the comment for Anniedale

The proper spelling of Anniedale SoC with 'e' in the middle. Fix typo in the
comment line in intel-family.h header.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/20170102092229.87036-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/include/asm/intel-family.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 34a46dc..8167fdb 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -57,7 +57,7 @@
 #define INTEL_FAM6_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
 #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* CherryTrail / Braswell */
 #define INTEL_FAM6_ATOM_MERRIFIELD	0x4A /* Tangier */
-#define INTEL_FAM6_ATOM_MOOREFIELD	0x5A /* Annidale */
+#define INTEL_FAM6_ATOM_MOOREFIELD	0x5A /* Anniedale */
 #define INTEL_FAM6_ATOM_GOLDMONT	0x5C
 #define INTEL_FAM6_ATOM_DENVERTON	0x5F /* Goldmont Microserver */