linux-kernel - Re: [PATCH] MIPS: NI 169445 board support

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Date:   Thu, 5 Jan 2017 18:33:53 +0000
From:   Joao Pinto <Joao.Pinto@...opsys.com>
To:     Niklas Cassel <niklas.cassel@...s.com>,
        Nathan Sullivan <nathan.sullivan@...com>,
        Ralf Baechle <ralf@...ux-mips.org>, <linux-mips@...ux-mips.org>
CC:     <davem@...emloft.net>, <netdev@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Lars Persson <larper@...s.com>,
        Joao Pinto <Joao.Pinto@...opsys.com>
Subject: Re: [PATCH] MIPS: NI 169445 board support

Hi,

Às 6:28 PM de 1/5/2017, Niklas Cassel escreveu:
> On 01/04/2017 05:38 PM, Nathan Sullivan wrote:
>> On Tue, Dec 20, 2016 at 05:34:34PM +0100, Ralf Baechle wrote:
>>> On Fri, Dec 02, 2016 at 09:42:09AM -0600, Nathan Sullivan wrote:
>>>> Date:   Fri, 2 Dec 2016 09:42:09 -0600
>>>> From: Nathan Sullivan <nathan.sullivan@...com>
>>>> To: ralf@...ux-mips.org, mark.rutland@....com, robh+dt@...nel.org
>>>> CC: linux-mips@...ux-mips.org, devicetree@...r.kernel.org,
>>>>  linux-kernel@...r.kernel.org, Nathan Sullivan <nathan.sullivan@...com>
>>>> Subject: [PATCH] MIPS: NI 169445 board support
>>>> Content-Type: text/plain
>>>>
>>>> Support the National Instruments 169445 board.
>>> Nathan,
>>>
>>> I assume you're going to repost the changes Rob asked for in
>>> https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.linux-2Dmips.org_patch_14641_-2326924&d=DgICaQ&c=DPL6_X_6JkXFx7AXWqB0tg&r=s2fO0hii0OGNOv9qQy_HRXy-xAJUD1NNoEcc3io_kx0&m=5p7f9dIkvVVK4UFHimMpezq5NwIJfUpd08c-Zk4_c6c&s=_JwSwe4VFYtxV1tcYt6Z8r4hJX0xfoGhCixygUxlg5s&e=  and resubmit?
>>>
>>> Thanks,
>>>
>>>   Ralf
>> Hmm, I found the issue with the generic MIPS config and dwc_eth_qos.  The NIC
>> driver attempts to cache align a descriptor ring using the ___cacheline_aligned
>> attribute on the descriptor struct, in combination with a "skip" feature in
>> hardware.  However, the skip feature only has a three bit field, and the generic
>> MIPS config selects MIPS_L1_CACHE_SHIFT_7.  So, the line size is 128, and with a
>> 64-bit bus, that means the NIC descriptor skip field would need to be set to
>> 14 to align the 16-byte descriptors...
>>
>> I guess it makes sense for a generic MIPS kernel to align everything for 128 byte
>> cache lines, and for me to fix the dwc_eth_qos driver to handle cases where the
>> line size is too big for the hardware skip feature, right?
> 
> I don't know if you've been following the discussion regarding
> dwc_eth_qos on netdev, but Joao Pinto from Synopsys is
> planning on removing the driver (since the stmmac driver
> now supports the same version of the IP, together with older
> versions of the IP).
> 
> Since device tree bindings are treated as an ABI,
> Joao has implemented a glue layer for stmmac that parses
> the dwc_eth_qos binding, but uses stmmac under the hood.
> 
> You can use any of the bindings, but since the dwc_eth_qos
> binding will be marked as deprecated, you might want to
> consider moving to the stmmac binding.

A patch set to port dwc_eth_qos to stmmac is at this moment under review:

http://patchwork.ozlabs.org/patch/711428/
http://patchwork.ozlabs.org/patch/711438/
http://patchwork.ozlabs.org/patch/711439/

Niklas has tested it and it works well, so after the patches are upstreamed the
dwc_eth_qos will be removed as agreed with Lars.

Thanks.

> 
>>
>> Thanks,
>>
>>    Nathan
>>
>>
>