linux-kernel - Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields

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Message-ID: <f4413bf1-56af-9912-7494-5cb633db835c@arm.com>
Date:   Fri, 6 Jan 2017 11:18:39 +0000
From:   Suzuki K Poulose <Suzuki.Poulose@....com>
To:     Catalin Marinas <catalin.marinas@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, mark.rutland@....com,
        ryan.arnold@...aro.org, sid@...erved-bit.com, aph@...hat.com,
        will.deacon@....com, linux-kernel@...r.kernel.org,
        adhemerval.zanella@...aro.org, dave.martin@....com
Subject: Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields

On 05/01/17 18:06, Catalin Marinas wrote:
> On Wed, Jan 04, 2017 at 05:49:05PM +0000, Suzuki K. Poulose wrote:
>> Track the user visible fields of a CPU feature register. This will be
>> used for exposing the value to the userspace. All the user visible
>> fields of a feature register will be passed on as it is, while the
>> others would be filled with their respective safe value.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will.deacon@....com>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
>
> Reviewed-by: Catalin Marinas <catalin.marinas@....com>
>
>> @@ -81,75 +82,75 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
>>
>>
>>  static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),

On a second look, I think we should make the RDM field visible to the user space as it
is something useful for the user.

>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
>
> BTW, as a separate patch I think we need to expose the RDM field in this
> register as well, together with a corresponding HWCAP bit.

OK, I will send a separate patch for this.

Thanks for the review.

Suzuki