linux-kernel - [PATCH v5 1/2] ARM: dts: vf610-zii-dev-rev-b: Remove leftover PWM pingroup

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Message-Id: <20170107200654.26056-1-andrew.smirnov@gmail.com>
Date:   Sat,  7 Jan 2017 12:06:53 -0800
From:   Andrey Smirnov <andrew.smirnov@...il.com>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     Andrey Smirnov <andrew.smirnov@...il.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Russell King <linux@...linux.org.uk>,
        Sascha Hauer <kernel@...gutronix.de>,
        Stefan Agner <stefan@...er.ch>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, andrew@...n.ch,
        Vivien Didelot <vivien.didelot@...oirfairelinux.com>,
        cphealy@...il.com
Subject: [PATCH v5 1/2] ARM: dts: vf610-zii-dev-rev-b: Remove leftover PWM pingroup

Remove pwm0grp since it is:

	a) Not referenced anywhere in the DTS file (unlike Tower board it
	is based on, this board does not use/expose FTM0)

	b) Configures PTB2 and PTB3 in a way that contradicts
	pinctrl-mdio-mux

Cc: Shawn Guo <shawnguo@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Russell King <linux@...linux.org.uk>
Cc: Sascha Hauer <kernel@...gutronix.de>
Cc: Stefan Agner <stefan@...er.ch>
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: andrew@...n.ch
Cc: Vivien Didelot <vivien.didelot@...oirfairelinux.com>
Cc: cphealy@...il.com
Tested-by: Nikita Yushchenko <nikita.yoush@...entembedded.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
---

No changes since v4

 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index fa19cfd..2210811 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -677,15 +677,6 @@
 		>;
 	};
 
-	pinctrl_pwm0: pwm0grp {
-		fsl,pins = <
-			VF610_PAD_PTB0__FTM0_CH0	0x1582
-			VF610_PAD_PTB1__FTM0_CH1	0x1582
-			VF610_PAD_PTB2__FTM0_CH2	0x1582
-			VF610_PAD_PTB3__FTM0_CH3	0x1582
-		>;
-	};
-
 	pinctrl_qspi0: qspi0grp {
 		fsl,pins = <
 			VF610_PAD_PTD7__QSPI0_B_QSCK	0x31c3
-- 
2.9.3