linux-kernel - Re: [PATCH v2 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CACRpkdZRLk1ZfUexM_y_RPKuRzcsSmWBo9e9VhvFNEFXF4xF-A@mail.gmail.com>
Date:   Tue, 10 Jan 2017 09:42:59 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     David Daney <ddaney@...iumnetworks.com>
Cc:     David Daney <ddaney.cavm@...il.com>,
        Alexandre Courbot <gnurou@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        David Daney <david.daney@...ium.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: gpio: Add binding documentation for gpio-thunderx

On Mon, Jan 9, 2017 at 8:44 PM, David Daney <ddaney@...iumnetworks.com> wrote:
> On 01/09/2017 11:36 AM, Linus Walleij wrote:

>>> +Optional Properties:
>>> +- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding
>>> is used.
>>> +- interrupt-controller: Marks the device node as an interrupt
>>> controller.
>>> +- #interrupt-cells: Must be present and have value of 2 if
>>> +                    "interrupt-controller" is present.
>>> +  - First cell is the GPIO pin number relative to the controller.
>>> +  - Second cell is triggering flags as defined in interrupts.txt.
>>
>>
>> AFAICT this device has an optional list of interrupts as well?
>> One per pin even?
>
> I'm not sure I understand your question.
>
> The GPIO hardware supports an interrupt on each pin.  The underlying
> interrupt mechanism is via PCI MSI-X, which are fully discoverable by the
> driver, so lack of device tree binding for the these underlying MSI-X is
> fully appropriate.

Sorry I guess I'm just ignorant about how PCI works, that has never
been my strongest subject admittedly.

So what you're saying is that PCI devices do not need specifying
interrupts not interrupt parents in the device tree?

That's fine then.

Yours,
Linus Walleij