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Message-ID: <CAD=FV=XWWt4tfEh0x7pHiCz8mzag3NLBzPO1Z9EPMQ=TxAK5Yw@mail.gmail.com>
Date: Mon, 9 Jan 2017 19:08:32 -0800
From: Doug Anderson <dianders@...gle.com>
To: Xing Zheng <zhengxing@...k-chips.com>
Cc: Heiko Stübner <heiko@...ech.de>,
"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Caesar Wang <wxt@...k-chips.com>,
Shawn Lin <shawn.lin@...k-chips.com>,
Brian Norris <briannorris@...omium.org>,
Jianqun Xu <jay.xu@...k-chips.com>,
Elaine Zhang <zhangqing@...k-chips.com>,
David Wu <david.wu@...k-chips.com>,
linux-clk <linux-clk@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for
RK3399 PMUCRU/CRU
Hi,
On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng <zhengxing@...k-chips.com> wrote:
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing pll rates are not changable, due to the missing pll lock status.
On rk3399 the GRF isn't used for pll lock status. It's used for PLL muxes.
...so technically if you don't include it then the PLL muxes won't be
changeable. Hopefully the code handles this if the property is listed
as "Optional". ...and unless Heiko says otherwise, you probably need
to list it as "Optional" since (presumably) there might be backward
compatibility issues.
-Doug
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