linux-kernel - Re: [PATCH v4 3/8] PCI: Don't block runtime PM for Thunderbolt host hotplug ports

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20170111100210.GL2330@lahna.fi.intel.com>
Date:   Wed, 11 Jan 2017 12:02:10 +0200
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Lukas Wunner <lukas@...ner.de>
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        linux-kernel@...r.kernel.org,
        Andreas Noever <andreas.noever@...il.com>,
        linux-pci@...r.kernel.org, linux-pm@...r.kernel.org,
        Chen Yu <yu.c.chen@...el.com>,
        Tomas Winkler <tomas.winkler@...el.com>,
        Amir Levy <amir.jer.levy@...el.com>,
        Bjorn Helgaas <helgaas@...nel.org>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
Subject: Re: [PATCH v4 3/8] PCI: Don't block runtime PM for Thunderbolt host
 hotplug ports

On Sun, Jan 08, 2017 at 09:41:45AM +0100, Lukas Wunner wrote:
> Hotplug ports generally block their parents from suspending to D3hot as
> otherwise their interrupts couldn't be delivered.
> 
> An exception are Thunderbolt host controllers:  They have a separate
> GPIO pin to side-band signal plug events even if the controller is
> powered down or its parent ports are suspended to D3.  They can be told
> apart from Thunderbolt controllers in attached devices by checking if
> they're situated below a non-Thunderbolt device (typically a root port,
> or the downstream port of a PCIe switch in the case of the MacPro6,1).
> 
> To enable runtime PM for Thunderbolt on the Mac, the downstream bridges
> of a host controller must not block runtime PM on the upstream bridge as
> power to the chip is only cut once the upstream bridge has suspended.
> Amend the condition in pci_dev_check_d3cold() accordingly.
> 
> Cc: Mika Westerberg <mika.westerberg@...ux.intel.com>
> Cc: Rafael J. Wysocki <rafael.j.wysocki@...el.com>
> Cc: Andreas Noever <andreas.noever@...il.com>
> Cc: Tomas Winkler <tomas.winkler@...el.com>
> Cc: Amir Levy <amir.jer.levy@...el.com>
> Signed-off-by: Lukas Wunner <lukas@...ner.de>
> ---
>  drivers/pci/pci.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 8ed098d..0b03fe7 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -2271,6 +2271,7 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>  
>  static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
>  {
> +	struct pci_dev *parent, *grandparent;
>  	bool *d3cold_ok = data;
>  
>  	if (/* The device needs to be allowed to go D3cold ... */
> @@ -2284,7 +2285,17 @@ static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
>  	    !pci_power_manageable(dev) ||
>  
>  	    /* Hotplug interrupts cannot be delivered if the link is down. */
> -	    dev->is_hotplug_bridge)
> +	    (dev->is_hotplug_bridge &&
> +
> +		/*
> +		 * Exception:  Thunderbolt host controllers have a pin to
> +		 * side-band signal plug events.  Their hotplug ports are
> +		 * recognizable by having a non-Thunderbolt device as
> +		 * grandparent.
> +		 */
> +		!(dev->is_thunderbolt && (parent = pci_upstream_bridge(dev)) &&
> +				 (grandparent = pci_upstream_bridge(parent)) &&
> +						!grandparent->is_thunderbolt)))

Can you move this to its own helper function?

>  
>  		*d3cold_ok = false;
>  
> -- 
> 2.11.0