linux-kernel - Re: [PATCH 1/2][UPDATE] of: base: add support to get the number of cache levels

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 12 Jan 2017 15:28:20 +0000
From:   Sudeep Holla <sudeep.holla@....com>
To:     Rob Herring <robh+dt@...nel.org>
Cc:     Sudeep Holla <sudeep.holla@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Tan Xiaojun <tanxiaojun@...wei.com>,
        Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH 1/2][UPDATE] of: base: add support to get the number of
 cache levels



On 12/01/17 13:24, Rob Herring wrote:
> On Tue, Jan 10, 2017 at 6:00 AM, Sudeep Holla <sudeep.holla@....com> wrote:
>> It is useful to have helper function just to get the number of cache
>> levels for a given logical cpu. This patch adds the support for the
>> same.
>>
>> It will be used on ARM64 platform where the device tree provides the
>> information for the additional non-architected/transparent/external
>> last level caches that are not integrated with the processors.
>>
>> Cc: Rob Herring <robh+dt@...nel.org>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Signed-off-by: Sudeep Holla <sudeep.holla@....com>
>> ---
>>  drivers/of/base.c  | 23 +++++++++++++++++++++++
>>  include/linux/of.h |  1 +
>>  2 files changed, 24 insertions(+)
>>

[...]

>> +int of_count_cache_levels(unsigned int cpu)
>> +{
>> +       int level = 0;
>> +       struct device_node *np = of_cpu_device_node_get(cpu);
>> +
>> +       while (np) {
>> +               level++;
> 
> This will return 1 if you have a cpu node and no cache nodes. Are you
> assuming the cpu has a cache?
> 

Ah right, that's completely wrong assumption.

> Perhaps you should just find the last level cache node and then just
> read "cache-level".
> 

Yes, sounds better. I will update accordingly. Thanks for the suggestion.

-- 
Regards,
Sudeep