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Message-ID: <609a80c7-9a85-2786-1e5a-a5c2340900b9@arm.com>
Date:   Fri, 13 Jan 2017 09:30:28 +0000
From:   Sudeep Holla <sudeep.holla@....com>
To:     Tan Xiaojun <tanxiaojun@...wei.com>,
        linux-arm-kernel@...ts.infradead.org
Cc:     Sudeep Holla <sudeep.holla@....com>,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH v2 2/2] arm64: cacheinfo: add support to override cache
 levels via device tree



On 13/01/17 09:06, Tan Xiaojun wrote:
> On 2017/1/13 2:29, Sudeep Holla wrote:
>> The cache hierarchy can be identified through Cache Level ID(CLIDR)
>> architected system register. However in some cases it will provide
>> only the number of cache levels that are integrated into the processor
>> itself. In other words, it can't provide any information about the
>> caches that are external and/or transparent.
>>
>> Some platforms require to export the information about all such external
>> caches to the userspace applications via the sysfs interface.
>>
>> This patch adds support to override the cache levels using device tree
>> to take such external non-architected caches into account.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: Will Deacon <will.deacon@....com>
>> Cc: Mark Rutland <mark.rutland@....com>
>> Signed-off-by: Sudeep Holla <sudeep.holla@....com>
> 
> Tested-by: Tan Xiaojun <tanxiaojun@...wei.com>
> 

Thanks for testing.

-- 
Regards,
Sudeep

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