linux-kernel - Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup

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Message-ID: <68f59de0-104f-41aa-886d-52d43ecd8e6b@synopsys.com>
Date:   Fri, 13 Jan 2017 16:34:26 +0000
From:   Joao Pinto <Joao.Pinto@...opsys.com>
To:     Kishon Vijay Abraham I <kishon@...com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Joao Pinto <Joao.Pinto@...opsys.com>,
        Arnd Bergmann <arnd@...db.de>
CC:     <linux-pci@...r.kernel.org>, <linux-doc@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-omap@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-samsung-soc@...r.kernel.org>,
        <linuxppc-dev@...ts.ozlabs.org>, <linux-arm-kernel@...s.com>,
        <linux-arm-msm@...r.kernel.org>, <nsekhar@...com>
Subject: Re: [PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr
 fixup


Hi Kishon,

Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Some platforms (like dra7xx) require only the least 28 bits of the
> corresponding 32 bit CPU address to be programmed in the address
> translation unit. This modified address is stored in io_base/mem_base/
> cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
> host mode where the address range is fixed, device mode requires
> different addresses to be programmed based on the host buffer address.
> Add a new ops to get the least 28 bits of the corresponding 32 bit
> CPU address and invoke it before programming the address translation
> unit.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
> ---
>  drivers/pci/dwc/pcie-designware.c |    3 +++
>  drivers/pci/dwc/pcie-designware.h |    1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index bed1999..d68bc7b 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -195,6 +195,9 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
>  {
>  	u32 retries, val;
>  
> +	if (pp->ops->cpu_addr_fixup)
> +		cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr);
> +
>  	if (pp->iatu_unroll_enabled) {
>  		dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
>  			lower_32_bits(cpu_addr));
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index a567ea2..32f4602 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -54,6 +54,7 @@ struct pcie_port {
>  };
>  
>  struct pcie_host_ops {
> +	u64 (*cpu_addr_fixup)(u64 cpu_addr);
>  	u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
>  	void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
>  	int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
> 

I think this is an acceptable fixup, I am ok with it.

Reviewed-By: Joao Pinto <jpinto@...opsys.com>

Joao