linux-kernel - Re: [linux-sunxi] [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

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Message-ID: <bcef274f-8342-bb6d-c086-4472596d8b73@megous.com>
Date:   Mon, 16 Jan 2017 23:57:46 +0100
From:   Ondřej Jirman <megous@...ous.com>
To:     icenowy@...c.xyz, Rob Herring <robh+dt@...nel.org>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Chen-Yu Tsai <wens@...e.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Bin Liu <b-liu@...com>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [linux-sunxi] [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in
 MUSB mode

Dne 16.1.2017 v 20:14 Icenowy Zheng napsal(a):
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
> 
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
> 
> Rename the register (according to its function and the name in BSP
> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> can support both peripheral and host mode (although the host mode of
> MUSB is buggy).
> 
> The register that is renamed is now unused, as its initial value is just
> MUSB mode. However, when OHCI/EHCI mode support is added, the register
> can be used again.
> 
> Signed-off-by: Icenowy Zheng <icenowy@...c.xyz>
> ---
>  drivers/phy/phy-sun4i-usb.c | 25 +++++++++----------------
>  1 file changed, 9 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index bf28a0fdd569..6b193a635c6b 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -49,7 +49,7 @@
>  #define REG_PHYBIST			0x08
>  #define REG_PHYTUNE			0x0c
>  #define REG_PHYCTL_A33			0x10
> -#define REG_PHY_UNK_H3			0x20
> +#define REG_PHY_OTGCTL			0x20

You have added REG_PHY_OTGCTL, but it is not used below.

regards,
  o.

>  #define REG_PMU_UNK1			0x10
>  
> @@ -269,23 +269,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>  		writel(val & ~2, phy->pmu + REG_PMU_UNK1);
>  	}
>  
> -	if (data->cfg->type == sun8i_h3_phy) {
> -		if (phy->index == 0) {
> -			val = readl(data->base + REG_PHY_UNK_H3);
> -			writel(val & ~1, data->base + REG_PHY_UNK_H3);
> -		}
> -	} else {
> -		/* Enable USB 45 Ohm resistor calibration */
> -		if (phy->index == 0)
> -			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> +	/* Enable USB 45 Ohm resistor calibration */
> +	if (phy->index == 0)
> +		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
>  
> -		/* Adjust PHY's magnitude and rate */
> -		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> +	/* Adjust PHY's magnitude and rate */
> +	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>  
> -		/* Disconnect threshold adjustment */
> -		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> -				    data->cfg->disc_thresh, 2);
> -	}
> +	/* Disconnect threshold adjustment */
> +	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> +			    data->cfg->disc_thresh, 2);
>  
>  	sun4i_usb_phy_passby(phy, 1);
>  
>