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Message-Id: <20170118202927.28740-8-f.fainelli@gmail.com>
Date:   Wed, 18 Jan 2017 12:29:26 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Russell King <linux@...linux.org.uk>,
        bcm-kernel-feedback-list@...adcom.com (maintainer:BROADCOM BCM7XXX ARM
        ARCHITECTURE), Jonathan Austin <jonathan.austin@....com>,
        Vladimir Murzin <vladimir.murzin@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Zhaoxiu Zeng <zhaoxiu.zeng@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        Nicolas Pitre <nico@...aro.org>,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Anna-Maria Gleixner <anna-maria@...utronix.de>,
        linux-kernel@...r.kernel.org (open list), will.deacon@....com
Subject: [PATCH 7/7] MAINTAINERS: Update brcmstb entries to cover B15 code

Update the brcmstb entry to cover the Broadcom Brahma-B15 processor
read-ahead cache support code.

Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c36976d3bd1a..47ee4a93d554 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2671,6 +2671,8 @@ S:	Maintained
 F:	arch/arm/mach-bcm/*brcmstb*
 F:	arch/arm/boot/dts/bcm7*.dts*
 F:	drivers/bus/brcmstb_gisb.c
+F:	arch/arm/mm/cache-b15-rac.c
+F:	arch/arm/include/asm/hardware/cache-b15-rac.h
 N:	brcmstb
 
 BROADCOM BMIPS MIPS ARCHITECTURE
-- 
2.9.3

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