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Message-ID: <1739624.bC7E8g3lgy@diego>
Date:   Wed, 18 Jan 2017 11:25:21 +0100
From:   Heiko Stübner <heiko@...ech.de>
To:     Xing Zheng <zhengxing@...k-chips.com>
Cc:     dianders@...gle.com, linux-rockchip@...ts.infradead.org,
        hl@...k-chips.com, Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng:
> The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.
> 
> Reported-by: Lin Huang <hl@...k-chips.com>
> Signed-off-by: Xing Zheng <zhengxing@...k-chips.com>

applied for 4.11 with Lin's test tag


Thanks
Heiko

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